IP-SDRAM/DDR2【PDF 8/106 页】IP DDR2 SDRAM CONTROLLER

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Sheet目录1220

4页 5页 6页 7页 [8页]9页 10页 11页 12页

1–4

■

Burst lengths:

Chapter 1: About This Compiler

Performance and Resource Utilization

■

■

2, 4, or 8, for DDR SDRAM

4, for DDR2 SDRAM

■

Banks:

■

■

4 for DDR SDRAM

4 or 8 for DDR2 SDRAM

■

Support for ODT in DDR2 SDRAM

Performance and Resource Utilization

Table 1–3 shows typical performance results for the DDR SDRAM controller using the

Quartus II software version 9.0.

Table 1–3. Typical Performance

System fMAX (MHz)

Device

Cyclone (EP1C20F400C6)

Cyclone II (EP2C35F672C6)

Stratix (EP1S25F780C5)

Stratix II (EP2S60F1020C3)

Stratix II GX (EP2SGX30CF780C3)

DDR SDRAM

133

167

200

200

200 (2)

DDR2 SDRAM

–

167

–

267 (1)

267 (1) (2)

Note to Table 1–3 :

(1) For information on a solution that achieves speeds greater than 267 MHz (533 Mbps) up to 333 MHz (667 Mbps),

contact your local Altera sales representative. To achieve speeds greater than 267 MHz, a new dynamic

autocalibration circuit is required.

(2) Pending device characterization.

f

For more information on device performance, refer to the relevant device handbook.

Table 1–4 shows typical sizes in logic elements (LEs) or adaptive look-up tables

(ALUTs) for the DDR SDRAM controller.

Table 1–4. Typical Size (Part 1 of 2) (Note 1)

Combinational

Device

Cyclone

Cyclone II

Memory Width (Bits)

16

32

16

32

64

72

LEs

860

1,050

940

1,120

1,500

1,600

ALUTs

—

—

—

—

—

—

Logic Registers

—

—

—

—

—

—

M4K RAM Blocks (2)

1

2

1

2

4

5

DDR and DDR2 SDRAM Controller Compiler User Guide

March 2009 Altera Corporation

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